Speech processing units, image processing units, computer systems equipped with a central processing unit (CPU), and the like require a large-capacity memory for the storage of data. This memory is desired to permit high-speed writing and reading and also to have a low production cost. As memories capable of satisfying these requirements, serial access memories are now receiving attention. They are introduced in "Variety of Field-Memory-Dedicated 1M Chips Now Available for VTRs and TVs" Nikkei Electronics, 421, 147-162, NIKKEI McGRAW-HILL, INC., May 18, 1987. To facilitate the understanding of the present invention, the construction and operation of a popular serial memory will hereinafter be described with reference to FIG. 1 through FIG. 4.
FIG. 1 is a simplified block diagram of the popular serial access memory. Different from general DRAMs, a serial access memory permits high-speed serial input and serial output without sequential input of Y addresses (column addresses). To continuously perform a serial output or serial input, the serial access memory has two memory banks A1,A2 of the same construction.
The memory banks A1,A2 are provided with (m,n) memory matrices 10-1,10-2, X addressing means 11-1,11-2 and serial access means 20-1,20-2, respectively. The memory matrices 10-1,10-2 have m word lines WL1-1 to WL1-m,WL2-1 to WL2-m and n bit lines BL1-1 to BL1-n, BL2-1 to BL2-n, respectively. Although not illustrated, there are memory cells disposed in the vicinity of intersections of the word lines and the bit lines and connected to the adjacent word lines and bit lines, respectively. These plural word lines WL1-1 to WL1-m,WL2-1 to WL2-m are selected by the X addressing means 11-1,11-2 which decode X addresses (row addresses). By this word line selection, unillustrated plural memory cells connected, for example, to the word lines WL1-j,WL2-j (j=natural number of 1-m) are electrically connected with adjacent bit lines BL1-1 to BL1-n, BL2-1 to BL2-n so that the plural memory cells are accessed by the serial access means 20-1,20-2 of n.times.1 bits which automatically generate serial addresses on the basis of a serial clock signal CLK. Incidentally, the respective bit lines BL1-1 to BL2-n are illustrated as single lines in FIG. 1 with a view toward simplifying their description. In truth, however, each bit line is formed of a pair of bit lines BL,BL which develop a potential in a complementary relation in an active state as illustrated in FIG. 2. The memory matrices 10-1,10-2 and X addressing means 11-1,11-2 of the serial access memory has substantially the same circuit construction and performs substantially the same circuit operation as conventional general-purpose memory circuits, for example, DRAM circuits, so that its further description is omitted. Using FIG. 2, the serial access means 20-1,20-2 in FIG. 1 will hereinafter be described in detail.
FIG. 2 is a circuit diagram of the serial access means 20-1,20-2 in FIG. 1.
The serial access means 20-1 has transfer means 21-1 to 21-1n which are connected to the plurality of paired bit lines BL1-1,BL1-1 to BL1-n,BL1-n of the memory matrix 10-1, respectively. The transfer means 21-11 to 21-1n are each composed of a pair of NMOS transistors. Describing in detail about the connection between the transfer means 21-11 and the paired bit lines BL1-1,BL1-1, a first electrode which is the source or drain of one of the NMOS transistors of the transfer means 21-11 is connected to one of the bit lines, i.e., the bit lines BL1-1 and a first electrode of the other NMOS transistor is connected to the other bit line BL1-1. The other transfer means is connected with its corresponding bit lines in a similar manner.
The gate electrodes of all the NMOS transistors of the transfer means 21-1 are commonly connected so that a signal Pt can be applied to all the gate electrodes practically at the same time to on-off control the NMOS transistors. When the signal Pt is high in level, all the NMOS transistors are in a conductive state so that the transfer means 21-11 to 21-1n can transfer the potentials of the respective paired bit lines BL1-1,BL1-1 to BL-n,BL1-n (hereinafter simply called "bit lines BL1-1 to BL-n38 for the sake of brevity) to a corresponding data register 22-1.
The data register 22-1 has the circuit construction that reverse parallel-connected two inverters are provided in sets as many as the number of the bit lines. The data register 22-1 has a function to temporarily hold data DA for the bit lines BL1-1 to BL1-n. Switching means 23-1 is composed of plural two-input NOR gates, which select pointer outputs responsive to the signal Pd, and plural data-transferring transistors which are on-off controlled by outputs of the two-input NOR gates.
Connected to an input side of the switching output 23-1 is a pointer 24-1, to which Y addressing means 27-1 is connected further. The pointer 24-1 is composed of plural elements 24-1.sub.1 to 24-1.sub.n which are in turn formed of groups of shift registers, and has a function to sequentially increment +1 by +1 by the clock signal CLK. The Y addressing means 27-1 has a function to decide the leading address of a serial access on the basis of Y addresses fed from a Y address bus 28 and is composed of plurality of elements 27-1.sub.1 to 27-1.sub.n.
The serial access means 20-2 is composed, like the serial access means 20-1, of transfer means 21-2 on-off controlled by the signal Pt, a data register 22-2, switching means 23-2 on-off controlled by the signal Pd to perform transfer of data DA, a pointer 24-2 composed of elements 24-2.sub.1 to 24-2.sub.n, and Y addressing means 27-2 composed of elements 27-2.sub.1 to 27-2.sub.2.
The elements 24-1.sub.1 to 24-1.sub.n,24-2.sub.1 to 24-2.sub.n of the pointers 24-1,24-2 are connected in the form of a ring through signal lines 25,26, so that each pointer output moves in a cyclic manner by the clock signal CLK.
FIG. 3(1) through FIG. 3(4) illustrate a serial read operation of FIG. 1, while FIG. 4(1) through FIG. 4(4) are concept diagrams showing a serial write operation (in-series writing operation) of FIG. 1.
In the read cycle shown in FIG. 3(1) through FIG. 3(4), to access the memory bank A1 during an access to the memory bank A2 in the serial access memory of FIG. 1, a word line WL1.sub.i on the memory matrix 10-1 is selected by the X addressing means 11-1 [FIG. 3(1)], and string data are transferred to the data register 22-1 through the bit line BL1 [FIG. 3(2)] (this is called "read transfer"). In the course of the subsequent access to the memory bank A1, the memory bank. A2 is prepared for the next access [FIG. 3(3) and FIG. 3(4)].
In the write cycle depicted in FIG. 4(1) through FIG. 4(4), the data DA which have been written in the data register 22-1 in advance are written in the memory matrix 10-1 during an access to the memory bank A2, said access being performed subsequent to completion of writing of data to the data register 22-1 of the memory bank A1 (this is called "write transfer") [FIG. 4(3)].
Speedup of an access is achieved by subjecting the memory matrices 10-1,10-2 and the serial access means 20-1,20-2 to a pipeline operation, that is, operating them alternately.
Incidentally, the Y addressing means 27-1 in FIG. 2 has a function to decide the leading address AD of a serial access. As soon as the leading address AD is decided, logical level "1" is set at any one of the elements 24-1.sub.1 to 24-1.sub.n,24-2.sub.1 to 24-2.sub.n of the pointers 24-1,24-2. By the clock signal CLK, this logical level is shifted 1 bit by 1 bit in an ascending order and moves in a cyclic manner through the signal lines 25,26, whereby a serial access is performed.
The serial access memory of the above construction is, however, accompanied by the problem to be described below.
The conventional serial access memory can access to successive data at a high speed by a pipeline operation. However, the pointers 24-1,24-2 which are adapted to generate serial addresses are shifted 1 bit by 1 bit in an ascending order by the clock signal CLK. When extraction, movement or the like of an image is conducted in image processing, for example, it is therefore impossible to skippingly access certain parts of a series of successive data, thereby making it unable to fetch them as a series of successive data or to write them as new data. This is disadvantageous and inconvenient in use.